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Description: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
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Size: 776597 |
Author: 汪旭 |
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Description: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
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Size: 895594 |
Author: 姚明 |
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Description: sdram的控制器 verilog源码
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Size: 719050 |
Author: 唐业衡 |
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Description: sdram controller.verilog
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Size: 13378 |
Author: 刘志刚 |
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Description: sdram控制器的开发程序,还有文档,可以参考以下
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Size: 776866 |
Author: 王鹏 |
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Description: Verilog&Vhdl混语言对SDRAM的控制源代码,提供了很好的例子,顶层文件为sdrm.v!-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
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Size: 250084 |
Author: 飞扬 |
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Description: 基于FPGA的SDRAM控制器设计
摘 要:介绍了SDRAM的特点和工作原理,提出了一种基于FPGA的SDRAM控制器设计方法,采用Verilog语言完成的控制器的设计,可以很方便地对SDRAM进行操作。控制器在大容量数据记录仪扩展缓存得到了很好的应用。
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Size: 245248 |
Author: 576974463@qq.com |
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Description: DDR(双速率)SDRAM控制器参考设计,xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
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Size: 131072 |
Author: 陈旭 |
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Description:
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Size: 19456 |
Author: 韩 |
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Description: 该程序是在xilinx的FPGA上实现DDR_SDRAM接口,程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
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Size: 23552 |
Author: 冯伟 |
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Description: Arm9指令Cache缓存模块的verilog代码,对一些做ARM硬件开发的朋友有参考价值。-Arm9 Instruction Cache Cache Module Verilog code, do some of the hardware development of the ARM friends reference value.
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Size: 3072 |
Author: 杨力 |
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Description: mt48lc4m32b2.v 是128M sdram 中典型设计。。可以借鉴。-mt48lc4m32b2.v 128M sdram is typical design. . Be used.
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Size: 8192 |
Author: chenliang |
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Description: DDR sdram 包含的完整的源码,仿真的相关文件-DDR sdram contains complete source code, simulation of the relevant documents
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Size: 1021952 |
Author: 飞翔 |
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Description: verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
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Size: 27648 |
Author: 王郁 |
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Description: sdram控制器,经过时序仿真,功能正确-SDRAM controller, after timing simulation, the correct function
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Size: 31744 |
Author: 雷峰成 |
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Description: The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated
with Micron SDRAM models. The design is verified with timing constraints at
115 MHZ.-err
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Size: 2628608 |
Author: ronsullivan |
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Description: verilog语言
利用FPGA控制SDRAM,相信很多朋友都需要
快下载吧-control FPGA Verilog language use SDRAM, believe that many of my friends need to download it faster
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Size: 19456 |
Author: 杜菲 |
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Description: SDRAM的Verilog HDL程序,适合DE2开发板,和TRDB-LCM显示器,很好哦-SDRAM procedures of the Verilog HDL for DE2 development board, and TRDB-LCM display, oh well
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Size: 4096 |
Author: 白雪 |
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Description: 可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的-Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of
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Size: 9216 |
Author: 郑宏超 |
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Description: 动态随即存储器的时序和工作原理,剖析了其运行的状态机,对底层程序开发有帮助(例子是关于HY57V641620)-Then the dynamic memory timing and working principle, analyzes the state machine its running on the bottom of program development helpful (example is the HY57V641620)
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Size: 432128 |
Author: hlc |
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